module a_module(
    input [31:0]        safe_buslines,
    input [`BUS_RANGE]  bus_lines_1,
    input [`BUS_RANGE]  bus_lines_2
);

    reg a;

    assign a = 1'h0;

    always @(posedge clk) begin

    end

    reg b;
    reg [7:0] vect;
    reg [7:0] vert [31:0];

    wire w_c;
    wire [7:0] w_vect;
    wire [7:0] w_mem [31:0];

    logic l_c;
    logic [7:0] l_vect;
    logic [7:0] l_mem [31:0];

    assign l_c = a;
endmodule

module b_module(
    input [31:0]        safe_buslines,
    input [`BUS_RANGE]  bus_lines_1,
    input [`BUS_RANGE]  bus_lines_2
);

    reg b;

    assign a = 1'h0;

    always @(posedge clk) begin

    end

    reg bb;
    reg [7:0] vectb;
    reg [7:0] vertb [31:0];

    wire w_cb;
    wire [7:0] w_vectb;
    wire [7:0] w_memb [31:0];

    logic l_c;
    logic [7:0] l_vect;
    logic [7:0] l_mem [31:0];

    assign l_c = a;

    a_module a_module(
        .safe_buslines(safe_buslines),
        .bus_lines_1(bus_lines_1),
        .bus_lines_2(bus_lines_2)
    )
endmodule
